Advantest (6857) Investor Update summary

Business environment and industry trends

• Semiconductors are integral to diverse applications, with AI and HPC driving demand for higher processing power and efficiency.

• Increasing device complexity and integration in HPC/AI, automotive, RF, and power devices is driving demand for advanced SoC testers.

• The industry faces interconnected challenges: scaling, power, memory, I/O, device complexity, and energy efficiency, all intensified by AI and advanced computing needs.

• Miniaturization, new process technologies, and 3D/2.5D/3.5D integration are accelerating complexity and requiring innovative test solutions.

Technological and testing challenges

• Increasing transistor counts, chiplet and multi-die integration, and complex packaging require more extensive and sophisticated testing, especially for HPC/AI devices.

• Testing must address multiple processor and IO dies, high-bandwidth memory, and rapid data transfer requirements.

• Miniaturization and new architectures introduce new failure modes, demanding additional test patterns and longer test times.

• Multi-die integration and thermal management are critical, as parallel testing generates significant heat.

• High reliability is essential, especially for data centers, necessitating stress and mission mode tests.

Evolution of test processes and scan test

• Scan test volume has surged in the 2020s, outpacing other test types due to exponential transistor growth and device complexity.

• Pattern generation efficiency has plateaued, making scan test the primary method despite longer test times.

• Built-in self-test (BIST) and DC tests have grown with increasing pin counts and device features.

• Test coverage now includes more mission mode, stress, and die-specific measurements.

• Additional test processes, such as die-level, multi-temperature, burn-in, and system-level tests, are being implemented to address new reliability and performance demands.