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Lokotech Group (LOKO) Investor Update summary

Event summary combining transcript, slides, and related documents.

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Investor Update summary

15 Oct, 2026

Business and product update

  • Transitioning from R&D to production for dual-use ASICs; engineering wafers are moving toward full-scale tape-out, with commercial production targeted for Q3 2025.

  • 12nm ASICs target 35%-80% lower energy consumption than competitors, with flexible form factors for mining and edge AI applications.

  • PowerPool acquisition supports profitable growth; November net revenue averaged EUR 3,400, with 2025 revenue projected at EUR 2.8 million under optimistic assumptions.

  • Edge AI ASIC use is being benchmarked and could become a significant revenue stream; licensing or joint ventures are possible.

  • Arctic Core data center business is expected to launch before year-end, offering conventional and secure data storage services.

Commercial agreements and market outlook

  • Flexible framework agreement signed; final order value depends on a second payment before production, and initial client interest is at the upper end of the range.

  • Targeting to double or replace current hash rate in a winner-takes-all market, representing a billion-dollar-plus addressable market.

  • Products target institutional miners and individual users, with a minimum order quantity of one blade.

  • Self-mining target is 8%-12% of total hash rate, supporting quality control and advanced RMA processes.

  • No debt except PowerPool seller's credit; strict R&D investment amortization and positive cash flow expected in 2025, driven by PowerPool.

Technical progress and competitive differentiation

  • Tape-out is on schedule, with 99% of chip area DRC-clean; GlobalFoundries selected as manufacturing partner and initial production capacity secured.

  • ASICs are more energy efficient than Bitmain’s 5nm chips and feature gradual degradation, a server-grade front-end PSU, and open USB plug-and-play protocol.

  • Reverse-engineering protections include physical chip safeguards, encrypted communication, and custom processor design.

  • Prototypes are mining for testing and validation, with scaled-up engineering wafers to follow.

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