Micron Technology (MU) Investor update summary

AI demand and memory architecture

• AI demand spans training, inference, agentic and physical AI: HBM per GPU rises 3.6x from H100 to B300; inference-server memory is projected to double in three years; agentic context grows 30x yearly; physical-AI DRAM exceeds 10x L2 cars for L4/robotaxis.

• Memory capability and architecture shape AI system capacity, performance and cost per token; inference uses HBM to feed processors, DRAM for working capacity and SSDs for retrieval data.

• Memory supply is expected to remain tight over the next two years, with no balance point anticipated; configurations and workload-specific optimization differ.

• Portfolio spans HBM, high-capacity DDR, low-power DRAM, data-center SSDs and NAND, with products for PCs, mobile, automotive, robotics and edge AI.

Products and milestones

• Shipped SOCAMM in Mar 2025 and sampled 1y-based 10.7 Gbps LPDDR5X in Jun 2025; shipped the PCIe Gen5 G9 QLC client SSD in Jan 2026 and Gen6 9650 SSD to mass production in Feb 2026.

• Announced HBM4 36 GB 12-high for high-volume manufacturing in Mar 2026 and shipped a 245 TB 6600 ION data-center SSD in May 2026; sampled 256 GB SOCAMM2 in Mar 2026.

• Qualified ASIL-B UFS 4.1 for automotive in Aug 2026 and sampled 512 GB DDR5 RDIMM, up to 9,200 MT/s, in Sep 2026.

• Leadership cited across four consecutive DRAM nodes, three HBM generations in power and three consecutive NAND nodes from G7 to G9; 1γ is in high-volume manufacturing.

• DRAM scaling has delivered >400x more bits per wafer since 1995; 1y dimensions fit >1,500 capacitors across a 50 μm hair.

DRAM roadmap

• 1δ is targeted for volume ramp in H2 2027, with mid-20s% bit-density improvement vs. 1y; it is designed for HBM5, vertical HBM and next-generation memory products.

• 1ε development is underway, with 1ζ and later nodes in pathfinding; 3D DRAM is a parallel roadmap, with deployment timing based on cost, complexity and performance.

• 6F² scaling continues; 4F² is not being pursued due to complexity and cost after more than two decades of investigation. DRAM bit density depends on capacitor pitch, not the cell label.

• LP6 targets >35% lower power than LP5 for some densities; DDR6 targets >2x DDR5 bandwidth. A 1 TB RDIMM generation is planned after the sampled 512 GB module.