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Cadence Design Systems (CDNS) investor relations material

Cadence Design Systems Goldman Sachs Communicopia + Technology Conference 2025 summary

Complete event summary combining all related documents: earnings call transcript, report, and slide presentation.
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Goldman Sachs Communicopia + Technology Conference 2025 summary9 Sep, 2025

AI and design innovation

  • AI is leveraged both to build AI systems and to enhance design tools, improving productivity and design quality, especially in power, performance, and area (PPA), with AI tools delivering up to half the benefit of a technology node shift.

  • Exponential growth in chip complexity and workload is expected to continue for at least the next decade, necessitating AI-driven productivity gains to keep pace.

  • AI and automation are increasing their share of R&D budgets, now approaching 11%, as companies seek to manage rising design complexity without proportional increases in engineering headcount.

Market trends and customer activity

  • Chip design activity is accelerating, with increased commitment from hyperscalers and system companies to develop their own silicon, driven by AI infrastructure and physical AI applications.

  • Revenue growth is supported by rising chip complexity and customer willingness to pay for value, with a focus on maximizing both revenue and operating margin.

  • The market for silicon is projected to reach $1.2 trillion by 2030 and $2.5 trillion by 2035, with both system and semiconductor companies expected to increase R&D investment.

Geographic and regulatory landscape

  • China revenue has stabilized after a brief EDA ban, now representing about 10-11% of total revenue, down from 17% a few years ago, with demand remaining strong and the regulatory environment currently stable.

  • The company is geographically and product diversified, reducing risk from regional disruptions.

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Next Cadence Design Systems earnings date

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Q3 202527 Oct, 2025
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Q3 202527 Oct, 2025

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Frequently asked questions

Cadence Design Systems, Inc. offers functional verification, logical equivalence checking, and formal verification solutions, as well as tools for emulation, prototyping, field programmable gate arrays, power management design, low power design and analysis, physical verification and signoff, analysis-driven debugging and side channel security defect detection. Cadence Design Systems also provides simulation and debugging products to facilitate hardware and software co-development of embedded computer systems, system level verification solutions that enable SoC verification prior to implementation, a family of emulation platforms with the capacity and performance of large ASICs and the ability to emulate a portion or all of an ASIC and scale to millions of gates. Cadence Design Systems, Inc. was incorporated in 1987 and is headquartered in San Jose, California.

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