VeriSilicon Microelectronics (Shanghai) (688521) investor relations material

Executive summary

• Q3 revenue reached RMB 1.317bn, up 28.16% QoQ and setting a record; 9M revenue was RMB 3.181bn, up 41.08% YoY.

• Backlog rose to RMB 18.569bn at September-end, while adjusted losses narrowed QoQ; guidance targets positive adjusted EBITDA in H2 2026 and positive adjusted net income for FY 2027.

Financial highlights

• Q3 attributable net loss was RMB 257.1m; adjusted attributable net loss was RMB 149.3m, narrowing RMB 34m QoQ.

• 9M attributable net loss was RMB 869.2m; adjusted attributable net loss was RMB 572.0m and adjusted EBITDA was negative RMB 271.8m.

• 9M gross profit rose 21.81% YoY to RMB 960m; gross margin was 30.18%, down 4.77 percentage points YoY amid revenue-mix changes.

• 9M R&D spending was RMB 1.407bn, up 42.06% YoY and 44.25% of revenue; Q3 spending rose 32.96% YoY to RMB 466.4m.

Outlook and guidance

• Adjusted EBITDA, excluding non-operating or non-cash expenses, is expected to turn positive in H2 2026; adjusted attributable net income is expected to turn positive for FY 2027.

• Management expects adjusted R&D expense as a share of revenue and gross profit to decline in H2 2026 and FY 2026, attributing the trend to business scale-up, not reduced R&D investment.

• Revenue conversion takes time: design-service orders generally require 9–12 months; production-service orders generally require 6–18 months, subject to customer shipment plans and foundry capacity.