4DS Memory (4DS) Investor Presentation summary

Technology overview and differentiation

• Developing high-speed, high-endurance, low-energy PCMO ReRAM bridging DRAM and Flash memory gaps.

• Area Based Interface Switching enables fast, tunable retention and high endurance, outperforming filamentary ReRAM.

• Demonstrated DRAM-speed write times, low energy per bit, and analog programmability.

• Scalable to advanced CMOS nodes, compatible with modern fabrication processes.

• Positioned for warm data, big data, and AI applications requiring persistent memory.

Commercial strategy and partnerships

• Strategic collaborations with imec, Infineon Technologies, and a top Taiwanese foundry.

• Infineon agreement covers a 15-month, $4.5M project to design a custom ReRAM test chip.

• Test chip development with Infineon accelerates commercial engagement and potential M&A.

• Licensing and M&A opportunities targeted post-validation of technology in partner systems.

• Value chain includes architecture, design, fabrication, and testing with leading industry partners.

Technical milestones and roadmap

• Achieved megabit array performance at DRAM speed with tunable retention and low energy.

• 5th Platform Lot: Process tuning for 20nm node, testing completion expected January 2025.

• 6th Platform Lot: Demonstration of 20nm node scalability, results due 1H 2025.

• Custom memory test chip with Infineon to be completed by H2 2026.

• Ongoing optimization with imec to support Infineon design and future commercial validation.